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PRELIMINARY TECHNICAL DATA
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Preliminary Technical Data
FEATURES 16-bit Resolution AD5545 14-bit Resolution AD5555 2 LSB INL AD5545 1, 1.5 LSB DNL AD5545 2mA Full Scale Current 20%, with VREF=10V 0.5s Settling Time 2Q Multiplying Reference-input 4Hz BW 3-Wire Interface Compact TSSOP-16 Package APPLICATIONS Automatic Test Equipment Instrumentation Digitally Controlled Calibration Industrial Control PLCs
GENERAL DESCRIPTION The AD5545, 16-bit, current-output, digital-to-analog converter is designed to operate from a single +5 volt supply. The applied external reference input voltage VREF determines the full-scale output-current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I to V precision amplifier. A serial-data interface offers high-speed, three-wire micro controller compatible inputs using serial-data-in (SDI), clock (CLK), and (CS). Additional LDAC function allows simultaneous update operation. The AD5545/AD5555 are packaged in the low profile compact TSSOP-16 package.
Dual, Current-Output Serial-Input, 16-/14-Bit DAC
AD5545/AD5555
VREFA VREFB
FUNCTIONAL DIAGRAMS
VDD
D0..Dx
16 or 14
RFBA
INPUT REGISTER R DAC A REGISTER DAC A R
SDI
IOUTA AGNDA RFBB
CS CLK
EN DAC A B ADDR DECODE
INPUT REGISTER
R
DAC B REGISTER
DAC B R
IOUTB AGNDB
POWER ON RESET
AD5545 AD5555
LDAC
DGNDF
RS MSB
ORDERING GUIDE
MODEL AD5545BRU AD5555CRU INL LSB 2 1 DNL LSB 1 1 RES (bits) 16 14 TEMP RANGE 40 / +85C 40 / +85C Package Description TSSOP-16 TSSOP-16 Package Option RU-16 RU-16
The AD5545 contains 3131 transistors. The die size measures xx mil X xx mil, xxxx sqmil.
REV. PrB, 18 FEB '2002 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com (c)Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD5545/AD5555
ELECTRICAL CHARACTERISTICS at VDD = 5V10% or VDD = 3V10%, VSS = 0V, IOUT = Virtual GND, GND=0V, VREF = 10V, TA = Full
Operating temperature Range, unless otherwise noted. PARAMETER SYMBOL CONDITION STATIC PERFORMANCE1 Resolution N AD5545, 1 LSB = VREF/216 = 153V when VREF = 10V Resolution N AD5555, 1 LSB = VREF/214 = 610V when VREF = 10V Relative Accuracy INL AD5545 Grade: B Relative Accuracy INL AD5555 Grade: C Differential Nonlinearity DNL Monotonic Output Leakage Current IOUT Data = 0000H, TA = 25C Output Leakage Current IOUT Data = 0000H, TA = TA MAX Full-Scale Gain Error GFSE Data = Full Scale Full-Scale Tempco2 TCVFS REFERENCE INPUT VREF Range VREF Input Resistance RREF Input Capacitance2 CREF ANALOG OUTPUT Output Current IOUT Data = Full Scale Output Capacitance2 COUT Code Dependent LOGIC INPUTS & OUTPUT Logic Input Low Voltage VIL Logic Input High Voltage VIH Input Leakage Current IIL Input Capacitance2 CIL 2, 3 INTERFACE TIMING Clock Input Frequency fCLK Clock Width High tCH Clock Width Low tCL CS to Clock Set Up tCSS Clock to CS Hold tCSH Data Setup tDS Data Hold tDH SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE Positive Supply Current IDD Logic Inputs = 0V Power Dissipation PDISS Logic Inputs = 0V Power Supply Sensitivity PSS VDD = 5% NOTES:
1. 2. 3. 4. All static performance tests (except IOUT) are performed in a closed loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25C These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5ns (10% to 90% of +3V) and timed from a voltage level of 1.5V. All AC Characteristic tests are performed in a closed loop system using an OP42 I-to-V converter amplifier.
5V10% 16 14 2 1 1 10 20 1/4 1 -12/+12 5 5 2 200 0.8 2.4 10 10 40 10 10 0 10 5 10 4.5/5.5 10 0.055 0.006
UNITS Bits Bits LSB max LSB max LSB max nA max nA max
mV typ/max
ppm/C typ V min/max k ohm typ4 pF typ mA typ pF typ V max V min A max pF max MHz ns min ns min ns min ns min ns min ns min V min/max A max mW max %/% max
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18 FEB '2002, REV. PrB
PRELIMINARY TECHNICAL DATA
AD5545/AD5555
ELECTRICAL CHARACTERISTICS at VDD = 5V10%, IOUT = Virtual GND, GND=0V, VREF = 10V,
TA = Full Operating Temperature Range, unless otherwise noted. PARAMETER AC CHARACTERISTICS Output Voltage Settling Time Reference Multiplying BW DAC Glitch Impulse Feed Through Error Digital Feed Through Total Harmonic Distortion Output Spot Noise Voltage NOTES:
1. 2. 3. 4.
SYMBOL tS BW Q VOUT/VREF Q THD eN
CONDITION To 0.1% of Full Scale, Data = Zero Scale to Full Scale to Zero Scale VREF = 5VP-P, Data = Full Scale VREF = 0V, Data Zero Scale to Mid Scale to Zero Scale Data = Zero Scale, VREF = 100mVrms, same channel CS = 1, and fCLK = 1MHz VREF = 5VP-P, Data = Full Scale, f=1KHz f = 1kHz, BW = 1Hz
5V10%
UNITS
0.5 4 7 -65 7 -73 4
s typ MHz typ nV-s typ dB nV-s typ dB typ nV/ rt Hz
All static performance tests (except IOUT) are performed in a closed loop system using an external precision OP177 I-to-V converter amplifier. The AD5545 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25C These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5ns (10% to 90% of +3V) and timed from a voltage level of 1.5V. All AC Characteristic tests are performed in a closed loop system using an OP42 I-to-V converter amplifier.
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................. -0.3V, +8V VREF to GND ...............................................................-18V, 18V Logic Inputs to GND................................................. -0.3V, +8V V(IOUT) to GND ...........................................-0.3V, VDD + 0.3V Input Current to Any Pin except Supplies........................ 50mA Package Power Dissipation .................... (TJ MAX - TA)/ THETAJA Thermal Resistance THETAJA 16-lead TSSOP........................................................ 150C/W Maximum Junction Temperature (TJ MAX) ........................ 150C Operating Temperature Range Models A, B, C ................................................-40C to +85C Storage Temperature Range ..............................-65C to +150C Lead Temperature: RU-16 (Vapor Phase, 60 secs) ................................... +215C RU-16 (Infrared, 15 secs)........................................... +220C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
RFBA VREFA IOUTA AGNDA AGNDB IOUTB VREFB RFBB 1 2 3 4 5 6 7 8 16 CLK 15 LDAC 14 MSB 13 VDD 12 DGND 11 CS 10 RS 9 SDI
REV. PrB, 18 FEB '2002
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PRELIMINARY TECHNICAL DATA
AD5545/AD5555
SDI CLK CS LDAC SDO
Figure 1. AD5545 Timing Diagram
A1 A0 D13 D12 D11 D10 D09 D08 D1 D0
INPUT REG LD
A1 A0 D15 D14 D13 D12 D11 D10
D1 D0
INPUT REG LD
tCSS
tDS
tDH
tCH
tCL tPD
tCSH t LDS tLDAC t LDH
SDI CLK CS LDAC
tCSS
tDS
tDH
tCH
tCL tPD
tCSH t LDS tLDAC t LDH
SDO
Figure 2. AD5555 Timing Diagram
Table 1. AD5545 Control-Logic Truth Table
CS
H L L L + H H H H H
CLK LDAC RS
X L + H L X X X X X H H H H H L H + H H H H H H H H H H L L
MSB
X X X X X X X X 0 H
Serial Shift Register Function
No Effect No Effect Shift-Register-Data advanced one bit No Effect No Effect No Effect No Effect No Effect No Effect No Effect
Input Register Function
Latched Latched Latched Latched Selected DAC Updated with current SR contents Latched Latched Latched Latched Data = 0000H Latched Data = 8000H
DAC Register
Latched Latched Latched Latched Latched Transparent Latched Latched Latched Data = 0000H Latched Data = 8000H
Table 2. AD5555 Control-Logic Truth Table
CS
H L L L + H H H H H Notes:
CLK LDAC RS
X L + H L X X X X X H H H H H L H + H H H H H H H H H H L L
MSB
X X X X X X X X 0 H
Serial Shift Register Function
No Effect No Effect Shift-Register-Data advanced one bit No Effect No Effect No Effect No Effect No Effect No Effect No Effect
Input Register Function
Latched Latched Latched Latched Selected DAC Updated with current SR contents Latched Latched Latched Latched Data = 0000H Latched Data = 2000H
DAC Register
Latched Latched Latched Latched Latched Transparent Latched Latched Latched Data = 0000H Latched Data = 2000H
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18 FEB '2002, REV. PrB
PRELIMINARY TECHNICAL DATA
AD5545/AD5555
1. 2. 3. SR = Shift Register + positive logic transition; X Don't Care At power ON both the Input Register and the DAC Register are loaded with all zeros. Table 3. AD5545 Serial Input Register Data Format, Data is loaded in the MSB-First Format. MSB LSB Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: Only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line's positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D15-D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any extra bits clocked into the AD5545 shift register are ignored, only the last 18 bits clocked in are used. If double buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC Registers. Table 4. AD5555 Serial Input Register Data Format, Data is loaded in the MSB-First Format. MSB LSB Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: Only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line's positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any extra bits clocked into the AD5555 shift register are ignored, only the last 16 bits clocked in are used. If double buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC Registers. Table 5. Address Decode:
A1 0 0 1 1 A0 0 1 0 1 DAC Decoded NONE DAC A DAC B DAC A and B
REV. PrB, 18 FEB '2002
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PRELIMINARY TECHNICAL DATA
AD5545/AD5555
AD5544/AD5554 PIN DESCRIPTION
PIN# Name 1 RFBA Function Establish voltage output for DAC A by connecting to external amplifier output DAC A Reference voltage input terminal. Establishes DAC A Full-Scale output voltage. Pin can be tied to VDD pin. DAC A current output. DAC A analog ground. DAC B analog ground. DAC B current output. DAC B Reference voltage input terminal. Establishes DAC B Full-Scale output voltage. Pin can be tied to VDD pin. Establish voltage output for DAC B by connecting to external amplifier output. Serial Data Input, input data loads directly into the shift register. Reset pin, active low input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for AD5545) and (2000H for AD5555) determined by the voltage on the 11 CS MSB pin. Register Data = 0000H when MSB = 0. Register Data = 8000H for AD5545 and 2000H for AD5555 when MSB = 1. Chip Select, active low input. Disables shift register loading when high. Transfers Serial Register Data to the Input Register when CS/LDAC returns High. Does not effect LDAC operation. Digital Ground Pin. Positive power supply input. Specified range of operation +5V10% or +3V10% MSB bit set pin during a reset pulse (RS) or at system power ON if tied to ground or VDD. Load DAC Register strobe, level sensitive active low. Transfers all Input Register data to DAC registers. Asynchronous active low input. See Control Logic Truth Table for operation. Clock input, positive edge clocks data into
2
VREFA
3 4 5 6 7
IOUTA AGNDA AGNDB IOUTB VREFB
12 13 14
DGND VDD MSB LDAC
15
8 9 10
RFBB SDI RS
16 CLK shift register.
CIRCUIT OPERATION
The AD5545/AD5555 contains a 16-/14-bit, current-output, digital-to-analog converter, a serial input register, and a DAC register. Both parts use a 3-wire serial data interface. D/A Converter Section The DAC architecture uses a current-steering R-2R ladder design. Figure 3 shows the typical equivalent DAC. The DAC contains a matching feedback resistor for use with an external I to V converter amplifier. The RFB pin is connected to the output of the external amplifier. The IOUT terminal is connected to the inverting input of the external amplifier. These DACs are designed to operate with both negative or positive reference voltages. The VDD power pin is only used by the logic to drive the DAC switches ON and OFF. Note that a matching switch is used in series with the internal 5 k feedback resistor. If users are attempting to measure the value of RFB, power must be applied to VDD in order to achieve continuity. The VREF input voltage and the digital data (D) loaded into the corresponding DAC register according to equation [1 &2] determines the DAC output voltage: VOUT = -VREF * D / 65,536 VOUT = -VREF * D / 16,384 Equation 1 Equation 2
R VREF 2R 2R 2R R 5 k S2 S1 R R
VDD RFB
IOUT GND
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY SWITCHES S1 & S2 ARE CLOSED, VDD MUST BE POWERED
Figure 3. Equivalent R-2R DAC Circuit These DACs are also designed to accommodate AC reference input signals. The AD5545 will accommodate input reference voltages in the range of -12 to +12 volts. The reference voltage inputs exhibit a constant nominal input-resistance value of 5K ohms, 30%. The DAC output (IOUT) is code-dependent producing various output resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the AD5545 on the amplifiers inverting input node. The feedback resistance in parallel with the DAC ladder resistance dominates output voltage noise. In order to maintain good analog performance, power supply bypassing of 0.01uF in parallel with 1uF is recommended. Under these conditions clean power supply voltages (low ripple, avoid switching supplies) appropriate for the application should be used. It is best to derive the AD5545's +5V supply from the systems analog supply voltages. (Don't use the digital 5V supply). See figure 4.
Note that the output full-scale polarity is opposite to the VREF polarity for DC reference voltages.
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18 FEB '2002, REV. PrB
PRELIMINARY TECHNICAL DATA
AD5545/AD5555
VIN +10.000V VOUT ADR01 R GND R VREF 2R 2R R 2R R R S2 VDD AD5545 5K +15V S1 IOUT VOUT VCC +15V 2R +5V ANALOG POWER SUPPLY
RFB
A1
GND DIGITAL INTERFACE CONNECTIONS OMITTED FOR SWITCHES S1 & S2 ARE CLOSED, DD MUST BE LOAD VEE
Figure 4. Recommended System Connections
SERIAL DATA INTERFACE The AD5545 uses a 3-wire (CS, SDI, CLK) serial data interface. New serial data is clocked into the serial input register in a 18bit data-word format. The MSB bit is loaded first. Table 2 defines the 18 data-word bits. Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data setup and data hold time requirements specified in the INTERFACE TIMING SPECIFICATIONS. Only the last 18-bits clocked into the serial register will be interrogated when the CS pin is strobed to transfer the serial register data to the DAC register. Since most micro controllers' output serial data in 8-bit bytes, three right justified data bytes can be written to the AD5545. After loading the serial register the rising edge of CS transfers the serial register data to the DAC register, during this strobe the CLK should not be toggled. ESD Protection Circuits All logic-input pins contain back-biased ESD protection Zeners connected to ground (GND) and VDD as shown in figure 7.
VDD DIGITAL INPUTS 5 k DGND
Figure 7. Equivalent ESD Protection Circuits
Mechanical Outline Dimensions
Dimensions shown in inches and (mm).
REV. PrB, 18 FEB '2002
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